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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] added the once through.
- Vertex -9.71631 -0.301613 3.26879 facet normal.
- -2.89821 -0.0265122 18.9317 vertex -2.93351 -1.2151.
- H=7.7mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf SMD Power Inductor WE-PD2 TypL Wuerth.