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Back(http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf HSOP 11.0x15.9mm Pitch 0.65mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf HSOP 11.0 x 15.9mm Pitch 0.65mm Slug Up (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf HSOP 11.0 x 15.9mm Pitch 0.65mm HSOP 11.0x15.9mm Pitch 1.27mm 50ohms AXICOM HF3-Series Relay Pitch 1.27mm Slug Up (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf HSOP, 54 Pin (https://www.nxp.com/docs/en/package-information/98ASA10506D.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket A-004 4 Knobs Screws, nuts, and spacers (see build notes) 1 SIP socket, 2.54 mm, 1x2 (see [build notes](build.md)) | | | | R16, R17, R19, R20 | 4 Hardware/PCB/precadsr/precadsr.sch | 247 (40 Dwgs.User user hide (0 "F.Cu" signal (31 B.Cu signal hide (31 B.Cu signal hide (31 B.Cu signal hide (33 F.Adhes user hide From 5a4d5850276107dae545a96ba13aec19af1bdbba Mon Sep 17 00:00:00 2001 Subject: [PATCH] couple more minor clearance tweaks Add ground fills, fix some clearance issues, add PCB slot, more options for this signature in database GPG Key ID: LICENSE Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/analogoutput.kicad_mod Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-NPTH.drl Normal file Unescape