Labels Milestones
Back\#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout.
- 2.880271e+000 2.464800e+001 facet normal.
- -0.0463745 0.880979 facet normal 4.225826e-001 1.881289e-003 9.063225e-001 vertex.
- -4.25372 9.04499 0.0456265 facet.