synth_tools

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(end 0.8 6 (end 1.8 1.8 (end -0.635 1.27 (end 1.27 -6.35 (end 1.27 -13.97 (end 2.286 1.016 (end -2.286 -1.016 (offset 0.254) hide (end 1.016 2.54 (end -1.016 -2.54 (offset 0) hide (length 0) hide (length 0) hide From d48d677c9103ec90137a6830434841a576342e9a Mon Sep 17 00:00:00 2001 Subject: [PATCH] Checkpoint after converting most things to SMD Latest commits for file PSU/PSU.md //clock rate (rv11 // 1 rotary switch, 5+ positions - 10 LEDs 3 sockets Subject: [PATCH] Added input resistor for sync; placed everything on PCB Added input resistor for sync; placed everything on PCB with exploratory 8hp layout PSU/Synth Mages Power Word Stun.kicad_prl | 6 Fireball/Fireball.kicad_sch | 48 dd8c61c34f A couple more GND-stitch vias eb8580ef62 Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs .../Unseen Servant/Unseen Servant.kicad_sch | 42 main MK_VCO/Panels/luther_triangle_vco_quentin_v3.scad 306 lines From 325d28022a5ac3ecda4a68ca826636c0d35a65a5 Mon Sep 17 00:00:00 2001 Subject: [PATCH] more fixes dcaec240831d28b722a7d7988287c76a1461e439 more fixes a5c5ff12ce18fecaaf346f973863d12bf361ac82 From 4d8e233e93a0e0142056dfcbd680a65973bd0ebb Mon Sep 17 00:00:00 2001 Subject: [PATCH] gets jiggy with PCB locator, 15 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator Hirose DF13 through hole, DF13-09P-1.25DS, 9 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator Soldered wire connection with feed through strain relief, for a 1uF capacitor. 1uF may be unnecessary, though. - C10, C14 too small.

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