Labels Milestones
BackHoles: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 11916 bytes .../Panels/MIRROR IMAGE.png | Bin 0 -> 4233424 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIN5.kicad_mod delete mode 100644 Hardware/PCB/precadsr/precadsr.cmp create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.gbrjob create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch deleted file mode 100644 Images/PXL_20210831_000949090.jpg create mode 100755 VCO_MANUAL_v2.pdf