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BackFile PSU/PSU.md Executable file View File Panels/fireball_vco_14hp_v1.scad Normal file Unescape Schematics/SynthMages.pretty/P160_pot_hole_nonpcb.kicad_mod Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-B_Mask.gbr Normal file View File Synth_Manuals/Kassutronics_Slope_Build_Docs_2.0A-1.pdf Normal file Unescape ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon.
- 1.005513e+02 7.486783e+00 vertex -9.047118e+01 1.008872e+02 6.078580e+00.
- Diode, 5KPW series, Axial, Horizontal.