Labels Milestones
Back-1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer F.Paste" "Notes": "Layer F.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer F.SilkS" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer F.SilkS" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 15:59:21 2021 ac58a9eaed checkpoint after roughing out middle PCB checkpoint.
- Normal -0.603867 0.370049 0.705981 facet normal.
- 0.0998673 0.114117 0.988435 facet normal -0.796849 -0.241718 0.553718.
- 3.931488e-002 facet normal -0.678848 -0.362853 -0.63836.
- Are merged with plated holes count.
- Relais Standex-Meder SIL-relais, Form 1A/1B, see https://standexelectronics.com/de/produkte/ms-reed-relais/ Standex.