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BackFiles fp-info-cache # Autorouter files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 12/13] Update Schematics/schematic_bugs_v1.md Clock POT is too.
- Pin pitch=15.3mm, 3W, length*width=16.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf Resistor Bare_Metal_Element.
- 2.508444e-15 1.449967e-15 -1.000000e+00 facet.
- 7.506481e-001 5.373734e+000 2.480400e+001 facet normal -0.115006 -0.000268624 0.993365.