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BackSW_SPDT_MSM SW 0 40 Y Y 1 F N DEF SW_Coded_SH-7040 SW 0 0 (add_net "/Pots, switches, misc/PUSH_1_P" (add_net "/Pots, switches, misc/PUSH_2_P" (format (units 2) (units_format 1) (precision 4 Schematics/MK_Schematic.png Normal file View File Schematics/notes.txt Normal file Unescape ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Minor layout tweaks From c6e6a61475df01d4832847208a59070c5a40c498 Mon Sep 17 00:00:00 2001 Subject: [PATCH 1/2] Fix rail clearance = ~11.675mm, top and bottom railHeight = (threeUHeight-panelOuterHeight)/2; mountSurfaceHeight = (panelOuterHeight-panelInnerHeight-railHeight*2)/2; hp=5.08; hwCubeWidth = holeWidth-mountHoleDiameter; offsetToMountHoleCenterY=mountSurfaceHeight/2; offsetToMountHoleCenterX=hp;//1hp margin on each side module.
- Vertex 2.847970e+000 4.867598e+000 9.983999e+000 vertex 6.971169e+000 -1.377601e+000.
- -4.444807e+000 2.491820e+001 facet normal 0.0754507 -0.766031 -0.63836.