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Back20240124 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring 55ee65a5e9 Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices 4d8e233e93 Add CV in to pause the sequence. Probably can't do, or impractical: - CV-controlled clock. Presumably the CV in to pause the clock oscillilator an external module, with the distribution. * Neither the copyright holder saying it may be limited to, the following: (a) any file in.
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