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Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 29479 bytes .../VALMORIFICATION+Build+and+BOM.pdf | Bin 684 -> 1394884 bytes Panels/title_test_18.stl | Bin 0 -> 406884 bytes ...uther_triangle_vco_quentin_v3_only_art.stl | Bin 0.

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