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Https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request 'new_footprints' (#5) from new_footprints into main Merge pull request synth_mages/MK_VCO#2 21e2abea62 Merge pull request 'Finish schematic, add PDF' (#2) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b 46614f2341 Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s bugfix/triangle_smoothness Forget (and ignore) fp-info-cache file as part of the section as a gate is present, or, if nothing is plugged into CLOCK. A notable issue with this design is ancient; maybe an updated one exists with current.

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