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As: Update README.md From abc39a50d6580d276015bcd974580f199a987534 Mon Sep 17 00:00:00 2001 Subject: [PATCH] checkpoint before getting really weird with WireIt A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from pcb_finalization into main 26b0f01955 Fix for component clearance, panel thickness from printer realities Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from pcb_finalization into main ... Put title box in PDF export' (#4) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file ad96459571a569a983e452184e49702fe8779c4e created pull request 'Finish schematic, add PDF | J6 | 1 | Conn_01x07 | \*(optional) SIP socket, 2.54 mm, 1x4 Pin header, 2.54 mm, 1x7 | | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1 | 10 nF Docs/precadsr.pdf | Bin 0 -> 193665 bytes Images/precadsr-panel.png | Bin 292501 -> 0 bytes 2 files.

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