synth_tools

Back

9.420201e-001 0.000000e+000 vertex -4.621885e+000 3.208877e+000 9.983999e+000 vertex 5.919638e+000 -3.953691e+000 2.496000e+001 vertex -4.091196e+000 3.859275e+000 9.983999e+000 vertex -1.481438e+000 5.423960e+000 2.496000e+001 vertex -7.061718e-001 -7.082244e+000 9.983999e+000 vertex 3.426833e-001 -7.112523e+000 9.983999e+000 vertex 4.427276e+000 5.493920e+000 9.983999e+000 vertex -5.605745e+000 6.171317e-001 1.747200e+001 facet normal 0.0816274 0.0817217 0.993307 vertex -1.05741 -5.51437 21.6407 facet normal 0.555568 -0.831471 -1.89274e-06 facet normal -0.14487 0.0600084 0.987629 vertex 4.51686 -0.737827 18.8084 vertex 4.47758 -0.23878 18.7299 facet normal 5.352688e-001 -8.446818e-001 0.000000e+000 vertex -1.209642e+000 5.491410e+000 1.747200e+001 facet normal 4.557469e-001 -7.833775e-001 4.226281e-001 vertex -7.455828e-001 5.347167e+000 2.475471e+001 facet normal -0.989347 -0.0973966 0.108199 facet normal 0.422682 -0.361949 0.830862 vertex -5.54554 4.83932 6.98393 facet normal -0.875976 -0.471404 0.102197 vertex 6.33525 -0.41258 7.82405 facet normal -0.180769 0.981021 -0.0701403 vertex 7.86658 3.78936 12.5141 facet normal -0.288584 -0.95132 0.108209 facet normal -0.727323 -0.241721 0.642318 facet normal 0.740023 0.60732 0.289014 facet normal 0.634593 0.772847 -1.35691e-05 facet normal -9.901828e-01 1.397735e-01 1.144797e-03 vertex -1.045318e+02 9.809589e+01 2.655000e+01 facet normal -0.768461 0.630682 0.108208 facet normal 4.747859e-001 -8.131037e-001 3.368097e-001 facet normal 3.176384e-001 1.414420e-003 9.482109e-001 vertex -4.165181e+000 -5.186868e-002 2.494118e+001 vertex 1.767937e+000 -5.074136e+000 2.494118e+001 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@gitlab.com:rsholmes/precadsr.git git submodule init git submodule init git submodule init git submodule update Find and replace last few thin traces, fix teardrops and gnd fill Embiggen traces, add teardrops main MK_SEQ/Schematics/Unseen Servant/Unseen Servant.kicad_pcb | 4 .../PCB/precadsr_Gerbers/precadsr-job.gbrjob | 128 .../precadsr_panel_al.kicad_pcb | 2510 .../Bigger_Push_Switch_Hole_NPTH.kicad_mod | 13 ...6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod | 39 ...L6.3mm_D2.5mm_P7.62mm_Horizontal.kicad_mod | 39 .../ao_tht.pretty/Rotary_Switch.kicad_mod | 38 .../ao_tht.pretty/Wall_wart_A-4118.kicad_mod | 28 .../ao_tht.pretty/analogoutput.kicad_mod | 213 .../ao_tht.pretty/analogoutput_12mm.kicad_mod | 210 Hardware/PCB/precadsr/fp-lib-table | 4 | 47k | Resistor | | C6, C7, C8, C9 | 1 | Conn_01x07 | *(optional) SIP socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x4 | | | | | | | | | | | | | S3 | 1 From 676d1403e60ef90e437a7e3e627a7211b04b0bb8 Mon Sep 17 00:00:00 2001 Panels/FIREBALL VCO.png Normal file Unescape "Name": "Top Solder Mask" "Name": "Bottom Solder Paste" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Mask" "Name": "Bottom.

New Pull Request

Labels Milestones