synth_tools

Back

Version; non Al panel Gerbers pts New KiCad version; non Al panel Gerbers Panels/10_step_seq.png Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Paste.gbr Normal file View File Panels/a_color_icon_of_a_flying_fireball.webp Normal file View File Schematics/Baby8_Part4_Cascading.pdf Normal file View File RadioShaek2Board.diy Executable file View File Hardware/PCB/precadsr_Gerbers/precadsr-Edge_Cuts.gbr Normal file View File Latest commits for file Docs/precadsr_layout_front.pdf Panels/dual_vca.scad Normal file Unescape Schematics/SynthMages.pretty/IDC-Header_2x05_P2.54mm_Vertical_Fixed_Ground_Fill.kicad_mod Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.kicad_sch Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Rotary_Switch.kicad_mod Normal file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Switch_Hole.kicad_mod Normal file View File Panels/futura medium condensed bt.ttf Normal file View File Latest commits for file Panels/FireballSpell_Large_bw.xcf Panels/10_step_seq.scad Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical.kicad_mod Normal file View File b404e3f9c5 Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 0 Minor layout tweaks merged pull request 'new_footprints' (#5) from new_footprints into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Finish schematic, add PDF Finish schematic, add PDF' (#2) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font so we don't need to call out for Wondermark fix; added Oatmeal initial Fix for two different ranges (e.g. 0-2.5v / 0-5v - Gate out (could normal to Reset In - diode to U2-3 - Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and the MCP4922 DAC (others may work). Probably can build our own based on it.

New Pull Request

Labels Milestones