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============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 From 54f1a61ba5f9983533e06b3eb1217b0ac5f22e05 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane Latest commits for file Schematics/shaek_try_1.diy Add kicad schematic, some diylc noodling Initial stab at a 10-step panel layout ideas Modules Index Pages Fab Plant Research Added four noteworthy fabs fcf4fb3bc8 Invisible Bread, Softer World (alt tags), Dinosaur Comics (alt.

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