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Back&& A.Net != B.Net" condition "A.Type == 'via' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Correcting changed filename in .prl gets jiggy with PCB trace layout Checkpoint in case of crashes Checkpoint in case you are implicitly allowing your code to be fixed elsewhere e49f4ab127dc081ee1c77dd21e80d128628a1152 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be 2cddc4d62d38c9e1b69839f92a19e7915eecbceb 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation main master PSU/Synth Mages Power Word Stun.kicad_pro 555 lines }, "silk_line_width": 0.15, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces a3181ad06b Add correct.
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