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Normal -2.890011e-001 4.954567e-001 8.191465e-001 vertex 8.339368e-001 -5.510304e+000 2.488700e+001 facet normal 8.191578e-001 2.377106e-003 5.735633e-001 vertex -5.052130e+000 1.988960e+000 2.480400e+001 facet normal -0.0497529 -0.0861751 -0.995037 vertex -3.08877 -9.50627 0.0451465 vertex -3.47906 -9.35243 0.0388323 facet normal 0.995195 -0.0979087 0 facet normal -4.851187e-001 -8.489573e-001 2.095978e-001 facet normal -0.0620422 -0.0777927 0.995037 vertex -5.86593 5.44279 19.9506 facet normal 7.741848e-01 1.163684e-03 -6.329586e-01 vertex -1.053126e+02 9.665134e+01 1.053895e+01 facet normal -0.884724 -0.268377 0.381099 facet normal 0.630746 0.768414 0.108161 facet normal -9.930271e-001 -4.114832e-003 1.178145e-001 vertex 4.025166e+000 2.304916e+000 2.467858e+001 facet normal -0.734373 -0.325742 0.595474 facet normal -0.847857 -0.479705 0.225879 facet normal 0.555568 -0.831471 -1.89274e-06 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md) How to use Latest commits for file Synth_Manuals/Module Summaries.ods Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main 3d279dd88c Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | | Tayda | A-2939 | | | | | | J6 | 1 nF | Unpolarized capacitor | | Tayda.

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