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Holes unplated through holes: unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Fireball/Fireball.kicad_dru Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-F_Mask.gbr Normal file Unescape DEF Kosmo_panel_Jack_Hole H 0 40 N N 1 F N.

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