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Back-2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in implement a DC offset via non-inverting op-amp. - A CV in controls the clock Add CV in to pause the clock feature/seq_chaining Checkpoint before trying to add glide Latest commits for file Schematics/notes.txt Add notes about UX component wiring initial notes for v1 build Schematics/bad_trace_v1.jpeg Normal file View File Synth_Manuals/Module Summaries.ods