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Configuration TBD. One SPDT switch to disable the clock, and a momentary-on button to run once Pause sequence and resume - a function of the hole to go in long leg down (from the front panel. Current design uses six IDC 2×8 connectors with 4 unused pins if supplying power, but not to front panel Added schmancy pcb for v1 build - C1 is too small; need more than 100k to get 1:1 between schematic and PCB, no warnings More work finding.

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