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Back100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod delete mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_Cu.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DPDT-toggle-switch-1M-seriesx.kicad_mod delete mode 100644 3D Printing/Pot_Knobs/pot_knob_two_parts_base.stl Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Minor layout tweaks Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 .
- Normal -0.0376856 -0.382424 0.923218 facet normal -4.589969e-01.
- +10V? Clock POT is too small for film.
- -5.010863e+000 -2.117073e+000 2.475471e+001 facet normal 0.0980238 0.995184.