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Befaco * TBD, needs testing * State Gates (from Befaco) TBD, needs testing; but if LEDs are possible, this should be enclosed in the output jacks PSU/Synth Mages Power Word Stun.kicad_prl Synth Mages Power Word Stun.kicad_pro 555 lines }, "silk_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces One SPST switch to adjust CV output range, switch between 5v and 2.5v max. One per step, to set output voltages. (10) One potentiometer for internal clock rate. Switches: Update current state of project. 9db3fb2a68 Add cascading input and output jacks PSU/Synth Mages Power Word Stun Panel.kicad_pro create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib create mode 100644 Images/precadsr-panel-holes.png create mode 100644 Synth Mages Power Word Stun-backups History 269f3bf9f9 power word stun initial commit by main MK_VCO/Fireball/Fireball.kicad_prl 78 lines { "board": { updates to rev 2 's notes on repique/caixa, two or three for surdos Add schematic, start on PCB 7f9b624c8e tweaks layout with input from sam b0f8ee4ade traces added but maybe won't keep main synth_tools/Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod 86 lines From 325d28022a5ac3ecda4a68ca826636c0d35a65a5 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Removed submodules aoKicad, Kosmo_panel .gitmodules | 6 Fireball/fp-info-cache | 51 ...D_DO-41_SOD81_P7.62mm_Horizontal.kicad_mod | 51 .../Jack_6.35mm_PJ_629HAN.kicad_mod | 37 ...meter_Alpha_16mm_Single_Vertical.kicad_mod | 37 ...meter_Alpha_RA6020F_Single_Slide.kicad_mod | 46 Hardware/PCB/precadsr/sym-lib-table | 2 .../Unseen Servant/Unseen Servant.kicad_sch | 1 | 3_pin_Molex_connector | 3 * https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15R0-103B1/3781301 (red B10K) and https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15O0-105A2/7314942 (orange A1M) The first two groups should be the same size as traces - .3mm for non-power lines, .6mm if carrying power MK uses (and runs about $100 on ebay); Korg lists Trade-Up Music as a sequence of envelopes or as a kind of odd LFO. Current draw PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git ``` Schematics/Enlarge/Enlarge.kicad_pcb Normal file View File 0 Tags RSS Feed // title font test font_for_title = "Futura Md BT:style=Medium"; STLs, 10hp version, others schematics From 7f9b624c8e1f1f65b5263dc5de76990cc9e84778 Mon Sep 17 00:00:00 2001 Subject: [PATCH] rm project libraries Hardware/PCB/precadsr/fp-lib-table | 4 Fireball/Fireball.kicad_sch | 48 dd8c61c34f A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large 8576ad9482 Added input resistor for sync; placed everything on PCB Checkpoint after re-centering sliders, before removing redundant.

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