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(grid_origin 121.92 119.38 "Notes": "Layer F.Paste" "Notes": "Layer B.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= 9060b76361734f9abf9a1c676dd9110e9ced917b Add MK manuals 77735c00cc3285131373f5cfc61b82eab5963d12 2cddc4d62d38c9e1b69839f92a19e7915eecbceb formatting caixa bits caixa_sr1.png | Bin QuentinEF.ttf => Panels/QuentinEF.ttf | Bin 11930 -> 0 bytes c58f541d7e.

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