3
1
Back

PG-DSO 12 pin, exposed pad, 4x4mm body, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 24 pin, exposed pad: 4.5x8.1mm, with thermal vias and counter-pad, see http://www.ti.com/lit/ds/symlink/tps62177.pdf WSON-10 package 2x3mm body, pitch 0.5mm, thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator JST EH series connector, B5PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator JST EH series connector, 53780-0270 (), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 24 Pin (JEDEC MO-153 Var BD.

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