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10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.kicad_pcb Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-B_SilkS.gbr Normal file Unescape From d433f7c09a85cc6fc15536169665e257a929b9f6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane Change transistor footprint to inline_wide, fix DRC ground plane on only one cross-board wire is needed.

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