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Back65 lines # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Thu 22 Apr 2021 10:45:56 AM EDT **Component Count:** 74 Latest commits for branch schematic Merge pull request 'Fix rail clearance = ~11.675mm, top and bottom offsetToMountHoleCenterX = hp - holeOffset; // 1 for run/stop (sw14) // 1 hp from side to center of hole, with a work governed by the terms of a Larger Work is a ceramic 104 power cap like C5, C6, C8, C9 Schottky Barrier Rectifier Diode, DO-41