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BackEb945be1-4d1d-46b5-b945-d4ebde74dae2) Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file again gets comfier with gitignore and git rm --cache 7130143159 learns about gitignore and git rm --cache learns about gitignore and git rm --cache 19116ba39d Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file 007cc05932 Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync to schematic, laid out PCB with on-board antenna Class 2 Bluetooth Module with on-board components PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces Using the Precision.
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