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BackF.Paste" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod Normal file View File Images/precadsr-panel.png Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_24.stl Executable file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_20.png Executable file View File Panels/luther_triangle_vco_quentin_v3_only_art.stl Normal file Unescape working_height = height.
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