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Done (including uploading gerbers Places to investigate. Note next to transistors to save on panel wires fewer_panel_wires Latest commits for file Images/PXL_20210831_000949090.jpg 2cb8e5eaf6 Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane Binary.

• Vertex 3.72964 9.00415 3.26879 vertex.
• 0.52861 0.0703598 vertex -8.35846 -7.75552 0.18985 facet.
• 9.628593e-01 facet normal 0.081929 -0.133699 0.98763.

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