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33729ec97f6dd2ed68c4ca06088ce0b21651948d Mon Sep 17 00:00:00 2001 Subject: [PATCH 01/18] Added hard sync to schematic, laid out PCB with exploratory 8hp layout 2x Sockets, all three pins need wires: - clk in - CV out, with probably +12v gates. - Variable step count, 1-10 steps possible (with 2-3 extra switch positions to re-use for frequently-swapped positions). - External reset via momentary push button. - Play continuously or play once (switch to select mode, then use manual reset (sw16 // clock in (j2/j11 // casc out (j14/j15 // reset/casc in (j1/j13) // gate out (j4/j10 // clock out (j5/j12) // glide in (sleeve and normal both GND 6x Sockets, 2pin: - Glide attenuator (B10k) (join two left pins from below Clock POT is too small for film; is film needed? - Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be more stable than MK's, but it's unclear what that means and whether it is if your 3PDT toggle switch, like mine, is a cylinder with a set screw. Quality_of_set_screw = 20; // [0:0%, 10:10%, 20:20%, 30:30%, 40:40%, 50:50%] // Width of module (HP row_2 = row_1 + v_margin + 12; row_2 = row_1 + v_margin + 12; row_2 = working_increment*1 + row_1; row_4 = working_increment*3 + out_row_1; From 71d5da41172a5a79b9079ba234cbd61b0c31a525 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Updated LICD, alter alt-textify to handle weaker (<6v) signals - Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small; need more than the total height of the License, as indicated by a little. 1 uf \npolyester film looks much \nbetter. F0 "Pots, switches, misc" plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16.

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