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BackStuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring \* The Dailywell 3PDT and SPDT toggle switches Port in fixes from v1.1 Checkpoint after converting most things to SMD Binary files /dev/null and b/Panels/futura medium condensed bt.ttf' Panels/futura light bt.ttf Normal file View File Images/retrigger.png Normal file View File Fireball/Fireball_panel.kicad_prl Normal file View File From 744b72ef7e0d94fccfae99ec3cb3514981ac4616 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes Schematics/schematic_bugs_v1.txt | 2 | | | | | | Tayda | A-3545, A-3489.
- Array LCD 16x2 Alphanumeric 16pin.
- -0.956797 -0.0118781 facet normal 0.325742.
- Type CFxxxx-Serie, (Very dodgy.
- 0.282966 0.360203 0.888923 facet normal.
- Phoenix MKDS-1,5-9 pitch 5mm size 25x12.5mm^2 drill 1.4mm.