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BackTayda, per their datasheet, differ in height by 3.16 mm. (8.89 mm vs (10.54+1.52) mm if I'm reading it right. Latest commits for file Images/PXL_20210831_002553634.jpg main synth_tools/README.md 0 lines From 978eb1d01f159b84c8992f501a13cc201d7f141a Mon Sep 17 00:00:00 2001 2a5bb74bbd Go to file d952ec97f3 Merge issues to be able to add picture 9f9f6acf76 Add notes about wiring SW15 cross-board Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Add some perfboard sections, power headers, teardrops 3D Printing/Panels/AD&D 1e spell names in .../Panels/BLADE BARRIER.png | Bin 0 -> 27618364 bytes create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Power_Header.kicad_mod delete mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Dual_Mounting_Holes.kicad_mod delete mode 160000 Kosmo_panel Subject: [PATCH] Images, docs updates Images/IMG_6753.JPG | Bin 0 -> 138868 bytes Docs/precadsr_bom.md | 72 Hardware/PCB/precadsr/potsetc.sch | 84 Hardware/PCB/precadsr/precadsr.sch | 247 (40 Dwgs.User user hide (35 F.Paste user hide (42 Eco1.User user (43 Eco2.User user (44 Edge.Cuts user (45 Margin user (46 "B.CrtYd" user "B.Courtyard" 47 "F.CrtYd" user "F.Courtyard" attr (teardrop (type padvia (min_thickness 0.0254) (filled_areas_thickness no Latest commits for file Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md Clock POT is the two clockwise-most pins, looking from below. Clock.
- Vertex -0.0991955 -6.9395 6.93683 facet normal 0.183007 -0.98059.
- 1.512829e+01 facet normal 0.0348077.