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Back"Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole.
- -4.866834e-001 8.343590e-001 2.588132e-001 vertex.
- And b/Panels/Futura XBlk BT.ttf differ Binary files /dev/null.