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BackVSON, 8 Pin (https://www.onsemi.com/pub/Collateral/NUF4401MN-D.PDF#page=6), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf Vishay PowerPAK SC70 dual transistor package http://www.vishay.com/docs/70486/70486.pdf TO-46-4 with Valox case, based on a regular polygon. ≥30 means "round, using current quality setting". // How much horizontal space needed for left-hand and right-hand sub-panels left_panel_width = 16.5+16.5+10.5; //two knob, one jack, plus space between them //left_panel_spacing = left_panel_width / 3 + tolerance*8; echo("Left panel:", left_panel_width, " with spacing ", left_panel_spacing); right_panel_width = width_mm - 10 - center_adjust; // build up seven rows; middle one unused row_1 = bottom_row + v_margin + 12; row_2 = row_1 + vertical_space/7; cv_in_1a = [left_col, row_2, 0]; cv_2b_atten = [right_col, row_5, 0]; cv_in_2a = [left_col, row_3, 0]; pwm_duty = [width_mm - h_margin - working_width/8, row_3, 0]; right_rib_x = width_mm - thickness*2.5 - tolerance*6; left_rib_x = hole_dist_side + thickness; col_left = thickness * 1.2; right_rib_x = width_mm - thickness*2; From 88bf85725f2c856b6f99f99568e61e08e1060d3b Mon Sep 17 00:00:00 2001 Subject: [PATCH] KiCad lib tables Hardware/Panel/precadsr-panel/fp-lib-table | 2 | 1N5817 | Schottky diode | | | D 2 pin Molex header 2.54 mm spacing | | | S1 | 1 | TL071 | Operational amplifier, DIP-8 | | | C12 | 3 | 10uF | Electrolytic capacitor | | | ----- | --- | ---- | ---- | | | | Tayda | A-962 | | | J5, J12, J13 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS), Switched T Pole (Normalling)