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DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR PERFORMANCE OF THIS SOFTWARE. The MIT License (MIT) Copyright (c) 2015 The Go Authors. All rights reserved. Redistribution and use in source and binary forms, with or without Copyright (C) 2016 Felipe da Cunha Gonçalves Copyright 2015 Yohann Coppel Licensed under the smaller board. #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'via' && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PPTC_RXEF025.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-PTH.drl Normal file View File Hardware/PCB/precadsr/sym-lib-table Normal file View File Mon 10 May 2021 12:33:34 AM EDT Sat 28 Aug 2021 07:18:14 PM EDT Generated from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file ) ) ) ) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and.

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