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Whether that is intentionally submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF | J6 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing 3 pin connector, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F215079%7FY1%7Fpdf%7FEnglish%7FENG_CD_215079_Y1.pdf%7F215079-4 connector TE-Connectivity Micro-MaTch Vertical 1-215079-2 8-215079-12 TE-Connectivity Micro-MaTch Vertical 1-215079-8 8-215079-18 TE-Connectivity Micro-MaTch female-on-board top-entry thru-hole 8 pin SIM connector for 1.6mm PCB's with 60 contacts (not polarized Highspeed card edge card connector socket for 1.57mm PCBs, vertical, alignment pins, weld tabs (source: https://suddendocs.samtec.com/prints/hsec8-1xxx-xx-xx-dv-x-xx-footprint.pdf 0.8 mm Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized Highspeed card edge connector for PCB's with 70 contacts (not polarized Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized Highspeed card edge connector for PCB's with 60 contacts (polarized Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized Highspeed card edge card connector socket for 2.36mm PCBs, vertical (source: https://suddendocs.samtec.com/prints/hsec8-1xxx-xx-xx-dv-x-xx-footprint.pdf 0.8 mm BGA-64, 10x10 raster, 10x10mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UCBGA-81, 9x9 raster, 3.639x3.971mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32f042k6.pdf WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 UCBGA-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ PowerPAK SO-8L Single (https://www.vishay.com/docs/64721/an913.pdf SOP, 16 Pin (https://www.ti.com/lit/ds/symlink/ts5v330.pdf#page=28 QFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_gullwing_generator.py TSOP I, 28 pins, surface mount PLCC, 20 pins, dual row male, vertical entry, strain relief clip Harwin Male Horizontal Surface Mount Fuse, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package (http://www.st.com/resource/en/datasheet/stm8s003f3.pdf ST UQFN 6 pin 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx Allegro Microsystems 12-Lead (10-Lead Populated) Quad Flat No-Lead Package, Body 4.4x6.5x1.1mm, Pad 3.0x4.2mm, Texas Instruments DSBGA BGA YZP R-XBGA-N6 Texas Instruments, DSBGA, 1.5195x1.5195x0.600mm, 8 ball 3x3 area grid, YBG pad definition, 0.704x1.054mm, 6 Ball, 2x3 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h725vg.pdf ST WLCSP-115, ST die ID 471, 4.437x4.456mm, 100 Ball, 10x10 Layout, 0.55mm Pitch, https://www.dialog-semiconductor.com/sites/default/files/da1469x_datasheet_3v1.pdf#page=740 VFBGA-100, 10x10, 7x7mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f302vc.pdf WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.5mm UFBGA-64, 8x8 raster, 3.357x3.657mm package, pitch 0.65mm WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.8mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.521x5.547mm package.

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