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9775036360 (https://katalog.we-online.com/em/datasheet/9775036360.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 32-Leads, Body 5x5x0.8mm, Pitch 0.5mm, Thermal Pad 3.1x3.1mm; (see Texas Instruments DSBGA BGA YZR0009 Texas Instruments, DSBGA, 1.36x1.86mm, 10 bump 3x4 (perimeter) array, NSMD pad definition Appendix A BGA 1156 1 FF1156 FFG1156 FFV1156 Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=307, NSMD pad definition Appendix A BGA 1760 1 FH1761 FHG1761 Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=294, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=90, NSMD pad definition Appendix A BGA 238 0.5 CP236 CPG236 Artix-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=306, NSMD pad definition Appendix A BGA 484 0.8 RS484 Artix-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A BGA 196 0.5 CPGA196 Artix-7 BGA, 19x19 grid, 10x10mm package, pitch 0.4mm; see section 6.2 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf TFBGA-100, 10x10, 9x9mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-64, 8x8 raster, 3.357x3.657mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152ze.pdf WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf WLP-9, 1.448x1.468mm, 9 Ball, 3x3 Layout, 0.4mm Pitch, http://www.st.com/content/ccc/resource/technical/document/technical_note/92/30/3c/a1/4c/bb/43/6f/DM00103228.pdf/files/DM00103228.pdf/jcr:content/translations/en.DM00103228.pdf pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf UFD Package, 4-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [QFN] with corner pads and trace routing to de-bodge the pots. 's notes on updating the fireball for rev 2 beta d89db83df13552281151487e636d3175f5aa0e7b updates to rev 2 beta d89db83df13552281151487e636d3175f5aa0e7b updates to rev 2 beta master Binary files /dev/null and b/Images/precadsr-panel-art.png differ Binary files /dev/null and b/Panels/futura medium bt.ttf | Bin 0 -> 12821 bytes 3D Printing/Rails/18hp_outie.stl | Bin 0 -> 16700 bytes .../Panels/SPIDER CLIMB.png | Bin 0 -> 13714 bytes .../precadsr-panel-Gerbers/precadsr-panel.drl | 47 .../precadsr_panel_al-F_Paste.gbr | 15 .../precadsr-panel-PasteTop.gtp | 15 .../precadsr_aux_Gerbers/precadsr-F_SilkS.gbr | 2066 .../precadsr_aux_Gerbers/precadsr-NPTH.drl | 17 .../fastestenv_Switch_Hole.kicad_mod | 17 .../Kosmo_LED_Hole.kicad_mod | 17 .../Kosmo_Trimmer_Pot_Hole.kicad_mod | 17 .../Kosmo_Trimmer_Pot_Hole.kicad_mod | 17 .../PCB/precadsr_Gerbers/precadsr-PTH.drl | 4 .../PCB/precadsr_Gerbers/precadsr-F_SilkS.gbr | 128 .../precadsr_aux_Gerbers/precadsr-B_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-F_Paste.gbr | 15 .../precadsr-panel-SilkBottom.gbo | 799 .../precadsr-panel-drl_map.pdf | Bin 36336 -> 0 bytes From d40f7ca1ca9e3e0f97e1dc4f553b9c659940a311 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add notes about UX component wiring Add notes about UX component wiring 9f9f6acf76f746b4755da71c07bb656091774052 SMT updates Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync (to a clock/gate/trigger input) Quantizer Interfaces to digital components and the following Secondary Licenses If You distribute must include a readable copy of.

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