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-3.462318e-04 vertex -9.521615e+01 1.057595e+02 2.550000e+00 facet normal 0.49996 0.866048 8.13718e-05 facet normal -0.0754488 0.766032 -0.63836 facet normal 0.741889 0.638745 0.203973 vertex -4.37272 5.83103 7.67586 vertex 7.22332 -1.01854 7.61242 facet normal 0.875976 -0.471404 0.102197 facet normal 0.990436 -0.097579 0.0975395 facet normal -0.29701 0.135092 0.94527 facet normal -0.366291 0.925196 0.0992094 facet normal 0.547914 0.449667 0.7054 vertex 5.04122 -7.99026 3.54602 vertex -9.31122 1.59974 3.54602 facet normal -0.135117 0.297038 0.945258 facet normal -0.29705 0.243786 0.923217 vertex 8.81743 -1.78758 3.82299 vertex -1 6.34847 12.858 vertex 1 7.29533 6.97071 vertex -1 7.30206 6.90928 vertex 1 6.42387 12.8506 vertex 1 6.28946 13.3638 vertex 1 7.23463 7.52583 vertex -1 6.3311 13.3597 vertex -1 7.26455 7.25222 vertex 1 7.16683 7.57523 vertex -1 7.23463 7.52583 vertex -1 3.18579 20.5 vertex 1 6.9437 7.89503 vertex 1 5.27986 22.0001 vertex -2.0582 4.96895 22.0001 vertex 1 7.30206 6.90928 vertex 1 7.16683 7.57523 vertex 1 6.43 13.35 vertex 1 3.18579 20.5 vertex -0.95 5.48429 22.5 vertex 0.95 4.22131 20.5 vertex 1 0 PCM_kikit Tab A symbol representing annotation for tab placement (condition "A.Type == 'track' && B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'track' && B.Type == 'track'" condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'track' && B.Type == A.Type && A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type && A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export' (#4) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main Merge pull request 'More schematics' (#3) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file Fireball/Fireball.kicad_dru | 102 Fireball/Fireball_panel.kicad_prl | 77 Schematics/Enlarge/Enlarge.kicad_pro | 475 create mode 100644.

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