3
1
Back

Tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints DRC; replace order number text replaces FIREBALL mask/etch with silkscreen Add footprint items for panel holes; separate panel and pcb into different files Add a front-panel PCB "net_color_mode": 1, "opacity": { More tweaks after pro review } ], "meta": { "version": 3 }, "net_colors": null, "netclass_assignments": null, updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing.

New Pull Request