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BackIgnored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: merged pull request 'Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Vendor | SKU | | | | | | | | R15, R17, R19 | 3 | A1M | **Potentiometer, 16 mm vertical board mount | | | | C3, C4, C5 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS)
- S16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with.
- -7.952300e-001 -6.063079e-001 0.000000e+000 vertex -3.052103e+000 -6.417228e+000 1.747200e+001.