Labels Milestones
Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Synth_Manuals/Module Summaries.ods.
- Path="/607ED812/60A9C088" Ref="R14" Part="1" AR.
- 3-lead though-hole mounted DIP package, row spacing.
- Size 45.7x8.45mm^2, drill diamater 1.3mm, pad.