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LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are.

• -0.946356 -0.307474 0.0993463 vertex -7.74866 -1.98952.
• 3.465027e+000 2.690868e+000 2.484855e+001 facet normal -0.555569.
• 3.5557e-06 facet normal -4.015069e-001 -7.030049e-001.

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