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Hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: unplated through holes: unplated through holes: merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main 26b0f01955 Fix for component clearance, panel thickness from printer .../luther_triangle_10hp_rib_space_fixes.stl | Bin 0 -> 136810 bytes Images/captest.png | Bin 0 -> 16700 bytes .../Panels/SPIDER CLIMB.png | Bin 0 -> 56316 bytes Binary files /dev/null and b/Docs/precadsr_layout_back.pdf differ Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/FIREBALL VCO.png differ Binary files /dev/null and b/Panels/FireballSpell.png differ Binary files.

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