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BackDrill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Synth_Manuals/LABOR_MANUAL.pdf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical_screw_centered.kicad_mod Normal file Unescape width = 17; // [1:1:84] working_height = height - v_margin*2 - title_font_size*1.5; saw_out = [third_col, third_row, 0]; fm_in = [first_col, first_row, 0]; sync_in = [first_col, fifth_row, 0]; square_out = [output_column, row_2, 0]; f_tune = [second_col, fifth_row, 0]; square_out = [output_column, row_2, 0]; fm_lvl = [second_col, first_row, 0]; //Second row interface placement f_tune = [second_col, first_row, 0]; //Second row interface placement sync_in = [first_col, first_row, 0]; c_tune = [width_mm/2 + h_margin, top_row, 0]; f_tune.
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