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Type="checkbox" disabled="" data-source-position="294" checked=""/>Reduce the font size to 9mm and align it precisely for repeatability b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane on only one side to center of hole, with a capacitor / resistor pair, see Fireball's hard sync to schematic, laid out PCB with exploratory 8hp layout Bring in diylc and openscad design Bring in diylc and openscad design Panels/dual_vca.scad | 393 create mode 100644 Fireball/Fireball.kicad_prl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Single_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Slotted_Mounting_Hole.kicad_mod delete mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp create mode 100755 VCO_MANUAL_v2.pdf Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2N3904 | 0.2A Ic, 40V Vce.

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