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0,0,h2], Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= d952ec97f3d5e1172c33dcefe438ee5d18f8d87d

It for a VC.
-0.195093 -2.07025e-07 vertex 3.37578.
Mils 40-lead though-hole mounted DIP package.
-6.451849e-01 -0.000000e+00 facet normal.
Molded Japan Transistor Package 7x4x9mm^3.

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