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RSS Feed From 3583986e89363c4a81b8aef8f93a5ec52c1c6cb4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] checkpoint after roughing out middle PCB ebf8c2dd87 Move LED resistors next to transistors to save on panel wires Update to 7.0, slider footprint From cf14a1432f34f59aa501c13fe7ffe5fdc817eb3a Mon Sep 17 00:00:00 2001 Subject: [PATCH] PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces One SPST switch per step, to enable/disable gate per step. (10 Momentary-normal-off pushbutton to manually reset. More repo cleanup, adopt github .gitignore file # Temporary files *.lck # Netlist files (exported from Eeschema # Autorouter files (exported from Pcbnew) Initial version \#* New KiCad version; non Al panel Gerbers Binary files /dev/null and b/Schematics/Luthers_VCO_schematic.pdf differ main MK_VCO/Fireball/Fireball.kicad_pcb 35767 lines da12ac6a39 Delete '3D Printing/Panels/FIREBALL VCO.png' 3D Printing/Panels/FIREBALL VCO.png | Bin 0 -> 31010 bytes Panels/label_test.stl | Bin 0 -> 87811 bytes sr1_full.png | Bin 0 -> 92229 bytes Panels/FireballSpellSmall.png | Bin 16561 -> 0 bytes From 811ef45c764021f623b8bb59234df1314fce4e91 Mon Sep 17 00:00:00 2001 Subject: [PATCH] tracks the ratsnest and compactifies the power subsystem From 9db3fb2a68fdc178fb3f74c68d22940f6cdd2e78 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update current state of project. Could make the hole on the larger board underneath the smaller board. #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'via'" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'via'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" condition.

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