Labels Milestones
BackSection 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf Texas Instruments, DSBGA, area grid, NSMD pad definition Appendix A BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 3x4 Layout, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf Plastic Small Outline (SS)-5.30 mm Body [SOIC], see https://ac-dc.power.com/sites/default/files/product-docs/senzero_family_datasheet.pdf Power-Integrations variant of 8-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads 12-lead though-hole mounted.