main MK_VCO/Fireball/Fireball_panel.kicad_pro 505 lines { "board": { updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing } ], "meta": { More tweaks after pro review 2 From 9e7b04561b8893062b3378503805ddd100c7260f Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix for component clearance, panel thickness from printer realities main synth_tools/Schematics/SynthMages.pretty/Switch.dcm 352 lines main synth_tools/Schematics/SynthMages.pretty/3.5mm_jack_hole_nonpcb.kicad_mod 24 lines Binary files /dev/null and b/Panels/FIREBALL VCO.png differ false XS3 FM CV From c852e5d6ad8630143a633f6c4ffcb4d705a43337 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Use THT electrolytics, finish SMT layout, try on quentin font for size Compare 2 commits » merged pull request synth_mages/MK_VCO#1 cfb5bfb128 Finish schematic, add PDF' (#2) from schematic into main Merge pull request 'Fix rail clearance issues, make all power traces large Added input resistor for sync; placed everything on PCB with on-board components c6741b48f0 More random files c6741b48f0ef8a6e69ecbca1a47bc4f4b481e2a3 Notes from MK's PCB livestream Footprints: - avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository https://github.com/holmesrichards/precadsr Submodules Latest commits for file README.md Latest commits for file caixa_sr1.png Image of caxia score Image of caxia score Fireball/Fireball.kicad_dru Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SPDT-toggle-switch-1M-series.kicad_mod Normal file View File Latest commits for file Panels/FireballSpellVertSmall.png From bacdac34d747275148c56e8293dc209c2e326fe4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete.